众文网1.常熟理工学院本三的本科学位要怎么才能拿到
修够学校规定的学分并修够满足要求的绩点即可拿到毕业证和学位证。
常熟理工学院是一所江苏省省属全日制本科院校，是教育部组织的新一轮本科教学合格评估的首所试点高校、“国家教育体制改革”试点高校、教育部“卓越工程师教育培养计划”试点高校、教育部信息化建设试点高校、江苏省首所省市共建试点高校。至今已为国家和社会培养了10万多名各类人才。学校坐落于人文荟萃、山明水秀的国家历史文化名城、国际花园城市——苏州常熟。学校现建有东湖和东南两个校区。
该校前身是创办于1958年的苏州师范专科学校和1984年建校的常熟职业大学，1989年两校合并为常熟高等专科学校。2001年江苏省人口学校并入。2004年5月12日，经中华人民共和国教育部批准在常熟高等专科学校基础上建立常熟理工学院。
截至2014年5月，该校占地面积1800亩，建筑面积63多万平方米，教学仪器设备资产总值2.23亿元，图书馆馆藏纸质文献142万余册。面向全国14个省招生，有普通全日制在校本科生18200多人，联合培养全日制研究生100多人，另有继续教育学院成人学历教育在籍学生6700多人。
2.谁做过FPGA与iic总线接口的设计,具体讲一下呗
IFPGA 模拟 IIC 接口的 Verilog HDL 设计 摘 要 串行扩展接口的发展是新一代单片机技术的显著特点†其中 I2C 总线功耗低†结构简单†使用灵活†被广泛应用于视频、音像等各类设备中。
本课题首先研究了 IIC 总线的规范†简要介绍了 Quartus Ⅱ设计平台†以及 FPGA 的设计流程。 在此基础上†重点介绍了 IIC 接口的总体设计方案†详细描述时序状态机的工作原理和 Verilog HDL 语言的实现†以及在 Quartus Ⅱ平台上的时序仿真。
本系统采用了自顶向下的设计方法†利用了 Verilog HDL 语言的结构描述风格†把整个设计分成 6 个模块†时钟分频模块†寄存器组模块†数据接收模块†数据发送模块†输出缓冲模块†时序控制模块†顶层模块也采用语言描述。 以 Altera 公司的 EPF10K10LC84‡4 器件为载体†设置相应的参数†在 QuartusⅡ平台上†实现系统的功能和仿真。
关键词ء现场可编程逻辑门阵列 IIC 总线 状态机 时序仿真 常熟理工学院毕业设计„论文• II IIC Interface with Verilog HDL Based On FPGA Abstract The development of expansion serial port interface is the distinguishing feature of Single-Chip Microcomputer technology of new generation。 It is widely used in the video-stereo equipments with its features of low power dissipations of buses, simple structure and flexible use。
Verilog HDL is considered as a core of digital system design and a key technique of implement digital system。 The design realizes the function of IIC bus interface on the FPGA。
At first the thesis deeply research IIC bus specification, then briefly introduce the Quartus II design environment and the design method, as well as FPGA design flow。 In this foundation, IIC bus interface design scheme, operational principle of the timing state, the implementation of Verilog HDL and the timing simulation under Quartus II is particularly introduced。
The system uses a top-down design methodology and the structure-describing style of Verilog language。 It is divided into 6 module, IIC_clock module, IIC_greg, IIC_rreg module, IIC_wreg module, IIC_tbuf and IIC_st module。
The top module is described by RTL level。 In order to test the function of the system, simulation environment is set。
Based on production EPF10K10LC84‡4 developed by ALTERA company, the project realize functional and timing simulation in the Quartus II development platform。 Key Words: FPGA; IIC bus; state machine; timing simulation 常熟理工学院毕业设计„论文• III目录 第一章 绪论 。
1 1。
1 IIC 总线的历史·················································································································1 1。 2 IIC 总线的优点·················································································································2 1。
3 FPGA 的发展与应用 ···········································································································2 1。 4 课题的主要工作及论文的组织 ························································································2 第二章 IIC 总线协议研究 。
3 2。1 IIC 总线概述 ····················································································································3 2。
1。1 IIC 总线简介 ·············································································································3 2。
1。2 IIC 总线的电气特性与结构 ············································。
转载请注明出处众文网 » 常熟理工学院毕业论文